The present invention relates to jitter attenuators.
Jitter attenuators are used to compensate for phase variations in an input signal. Uncompensated jitter can be a significant source of error. In transmission systems such as T1 and E1, the clock is encoded with the data. A receiver will extract the clock from the coded datastream and provide the extracted clock and data itself. This clock can then be used to retransmit the data to the next node. Jitter is obviously undesirable since any phase variation of the clock can be passed along from node to node.
There are many causes of jitter. For example, the transmission media may transmit higher frequency portions of the signal faster than lower frequency portions.
Typically, the received clock is filtered and smoothed to remove the jitter. An elastic buffer, such as a FIFO, is sometimes used to buffer the difference in rates of the received jittery clock and the retransmitted data. See, for example, U.S. Pat. No. 5,090,025.
Another example of a jitter attenuator is shown in U.S. Pat. No. 5,495,243. This patent shows using an up/down counter and a subsequent decoder to control the digital frequency synthesizer. The input clock is used to decrement the counter, while the output, divided-down clock is used to increment the counter. Each change in the count causes a change in the phase of the synthesized frequency.
It would be desirable to have a digital jitter attenuator which corrects for jitter, but which corrects slowly enough to avoid tracking phase variations which are transient.
The present invention provides a phase detector which detects the phase difference between the input clock and an output clock. That phase difference is used to gate a high frequency clock, which is provided to the clock input of an up/down counter. The phase detector also indicates whether the phase difference is positive or negative. When the counter reaches a pre-specified up or down count, an advance or retard signal is provided to a phase selector. The phase selector selects one of multiple phases of a clock used for the output clock.
To the extent jitter is self-offsetting, or corrects it on the next or a close pulse, the present invention will not change the output phase. For example, a positive count may be offset by a subsequent negative count. It is only when the total count reaches a preselected number that the output clock phase is adjusted. This ensures that the phase jitter is not transient. However, the count is selected low enough so that true jitter is compensated for sufficiently quickly.
In a preferred embodiment, the invention uses a multiple phase clock generator. One of the clock phases generated is selected by a phase selector connected to the output of the up/down counter. The selected clock is then divided down to the frequency of the input clock. The same high frequency clock used to generate the multiple phases is also used for the input phase detector.
For a further understanding of the nature and advantages of the invention, reference should be made to the following description taken in conjunction with the accompanying drawings.